1. Field of the Invention
The present invention relates to a dynamic random access memory (hereafter referred to as xe2x80x9cDRAMxe2x80x9d) which must be refreshed in order to hold data.
2. Description of the Related Art
A DRAM with a large memory capacity is normally provided with a memory cell array constituted of a plurality of memory blocks for data storage. As various mobile products with battery-driven systems have become distributed in ever-increasing numbers in the market in recent years, it has become necessary for DRAM installed in such systems to operate at a lower voltage level and achieve lower power consumption.
The structure of memory cells in DRAM require a refresh operation be performed in order to hold data stored in memory. The refresh operation must be performed continually as long as the stored data are to be sustained, regardless of whether they apparatus or the system in which the DRAM is installed is in an active state or a suspended state.
FIG. 2 is a block diagram of a self refresh control circuit in a DRAM in the prior art.
DRAM in the prior art is provided with a self refresh control circuit, as illustrated in FIG. 2 to achieve self refresh.
Self refresh in the DRAM refers to a refresh operation performed by using a row address strobe signal RASB (the xe2x80x9cBxe2x80x9d at the end of the code indicates the anti-phase) that, when set to xe2x80x9cLxe2x80x9d, indicates an active state, and a column address strobe signal CASB that, when set to xe2x80x9cLxe2x80x9d, indicates an active state. The refresh is performed when the signal CASB set to xe2x80x9cLxe2x80x9d after the setup time elapses has been held at xe2x80x9cLxe2x80x9d over a specific length of time or longer before the signal RASB is set to xe2x80x9cLxe2x80x9d.
The self refresh control circuit is provided with a refresh decision-making circuit 3 connected to an RASB pad 1, through which the signal RASB is input, and a CASB pad 2, through which the signal CASB is input. The refresh decision-making circuit 3 makes a decision as to whether or not a self refresh is requested based upon the signal RASB and the signal CASB, and accordingly generates a refresh enable signal SREF. The output side of the refresh decision-making circuit 3 is connected to a refresh timer 4, a refresh control circuit 5, a refresh counter 6 and an X address buffer 7.
The refresh timer 4, which is activated by the signal SREF, has a function of providing a refresh request signal RREQ to be used as a timing signal to the refresh control circuit 5. The refresh counter 6, which is activated by the signal SREF, generates a refresh address RA (0:i) with an (i+1) bit width for a refresh based upon a counter control clock RCLK. The refresh control circuit 5, which is activated by the signal SREF, outputs an RAS signal for internal use (hereafter referred to as an internal RAS) based upon the signal RREQ, with its output side connected to one of the input terminals of a two-input NOR gate 8 via a node N1. The other input terminal of the NOR gate 8 is connected to the signal RASB pad 1, and the output terminal of the NOR gate 8 is connected to an RAS system circuit 11 via two-stage inverters 9 and 10.
The RAS system circuit 11, which is constituted of a sense amplifier that amplifies the potential difference between individual bit lines BL and BLB in a bit line pair, a timing generator that generates a timing signal (neither shown) and the like, provides the counter control clock RCLK to the refresh counter 6 and provides an X address latch signal LH to the X address buffer 7.
An X address AX (0:i) for normal access is input to the X address buffer 7 through an address pad 12. When the signal SREF is set to xe2x80x9cHxe2x80x9d, the refresh address RA (0:i) is stored, whereas the X address AX (0:i) is stored if the signal SREF is at xe2x80x9cLxe2x80x9d. An X pre-decoder 13 and a plurality of X decoders 14-1 , 14-2, . . . are connected to the output side of the X address buffer 7. The X pre-decoder 13 decodes the address stored at the X address buffer 7 to select a memory block, and outputs the X address corresponding to the selected memory block as a pre-decode signal, which is then provided to the X decoders 14-1, 14-2, . . . One of the X decoders 14-1, 14-2 . . . is selected by the pre-decode signal, and the pre-decode signal is then decoded by the selected X decoder to select a word line WL of the memory block connected to the X decoder.
FIG. 3 is a waveform diagram corresponding to the operation explained in reference to FIG. 2. In reference to FIG. 3, the self refresh operation is summarized.
Based upon the signal RASB and the signal CASB, the refresh decision-making circuit 3 generates a refresh enable signal SREF at xe2x80x9cHxe2x80x9d. When the signal SREF is at xe2x80x9cHxe2x80x9d, the refresh timer 4 automatically sets the refresh request signal RREQ to xe2x80x9cHxe2x80x9d intermittently. Thus, the internal RAS provided to the RAS system circuit 11 alternates between H and L repeatedly. The RAS system circuit 11 provides the counter control clock RCLK to the refresh counter 6, and the refresh counter 6 sequentially outputs the refresh addresses RA (0:i) in synchronization with the counter control clock RCLK. As a result, the refresh addresses RA (0:i) are stored at the X address buffer 7, and the refresh addresses RA (0:i) are decoded by the X pre-decoder 13 and the X decoders 14-1, 14-2 . . . In addition, the word line WL at the selected memory block is selected and the memory cells (not shown) connected to the word line WL become refreshed. This self refresh operation is repeated as long as the signals RASB and CASB remain at xe2x80x9cLxe2x80x9d.
However, the following problem is yet to be addressed with regard to the DRAM in the prior art.
FIG. 4 illustrates the problem of the DRAM in the prior art.
A plurality of memory cells in the DRAM are constituted as, for instance, two 256 kilo-bit (256 kb) memory cell array blocks ABLK1 and ABLK2. Word lines WL inside the individual blocks ABLK1 and ABLK2 are respectively selected by the X decoders 14-1 and 14-2, and bit line pairs BL and BLB inside the two blocks ABLK1 and ABLK2 are selected by a common Y decoder 15. It is assumed that either one of the blocks ABLK1 or ABLK2 is selected in correspondence to the levels of the highest-order bit signal A8X and the X address AX (0:i) and a signal A8XB at the anti-phase of the signal A8X. The signals A8X and A8XB are pre-decoded by the X predecoder 13, and either one of the two blocks ABLK1 and ABLK2 is selected. The one block ABLK1 or ABLK2 selected by the signals A8X and A8XB in this process is a block that is not required to hold data. Since both blocks ABLK1 and ABLK2 undergo the self refresh process regardless of whether or not they need to hold data, power is consumed in a wasteful manner, and thus, it does not satisfy the technological requirement of lower power consumption.
For instance, when the DRAM is utilized to store messages in a mobile telephone or the like, while it is necessary to perform a self refresh for the block (e.g., the block ABLK1) having messages stored therein, the other block ABLK2 does not need to be refreshed. However, since a self refresh is performed for the block ABLK2 which does not need to be rereshed as well in the DRAM in the prior art, battery power is unnecessarily depleted.
In order to address the problem of the prior art discussed above, in a first aspect of the present invention, a DRAM comprising a plurality of blocks each provided with a plurality of word lines selected by an X address, a plurality of bit lines and a plurality of memory cells for data storage connected to the word lines and the bit lines, a refresh decision-making circuit that detects whether or not a refresh is requested for the plurality of memory cells based upon a control signal provided from the outside and makes a decision with regard to its mode, a refresh timer that is activated when the result of the decision-making performed by the refresh decision-making circuit indicate a self refresh mode to generate a timing signal, a generator that generates a counter control clock that is synchronous with the timing signal, a refresh counter that is activated when the result of the decision-making performed by the refresh decision-making circuit indicate the self refresh mode to generate and output a refresh address for a refresh in synchronization with the counter control clock and an X address buffer that stores the refresh address when the result of the decision-making performed by the refresh decision-making circuit indicates the self refresh mode and stores an X address provided from the outside when the result of the decision-making performed by the refresh decision-making circuit do not indicate the self refresh mode, is provided.
The DRAM according to the present invention is further provided with a means for latching that latches block selection information provided from the outside with specific timing indicating whether not a refresh needs to be performed for the block, an X pre-decoder that pre-decodes the address stored in the X address buffer to select the block and outputs a pre-decode signal containing the selection information, an X decoder that decodes the pre-decode signal and selects a word line corresponding to the memory cells within the block selected by the X pre-decoder, a means for operation prohibition that compares the block selection information latched by the means for latching with the refresh address and prohibits operation of the generator if the refresh address indicates a block that does not need to be refreshed and a means for clock route changing that provides the timing signal to the refresh counter instead of the counter control clock when the operation of the generator is prohibited.
In a second aspect, a DRAM having the plurality of blocks, the refresh decision-making circuit, the refresh timer, the generator, the refresh counter, the X address buffer, the means for latching, the X pre-decoder and the X decoder in the DRAM in the first aspect is provided. The X pre-decoder in the second aspect compares the block selection information latched by the means for latching with the refresh address stored at the X address buffer when the result of the decision-making performed by the refresh decision-making circuit indicate the self refresh mode, outputs a pre-decode signal at a first potential containing information indicating a block specified by the refresh address that needs to be refreshed and sets the pre-decode signal to a second potential if the refresh address specifies a block that does not need to be refreshed. In addition, the X decoder decodes the pre-decode signal at the first potential output by the X pre-decoder to select a word line corresponding to the memory cells within the block specified by the X pre-decoder, whereas the word line selection operation is prohibited if the pre-decode signal is set to the second potential.
In a third aspect, a DRAM comprising a plurality of blocks each provided with a plurality of word lines selected by an X address, a plurality of bit lines and a plurality of memory cells for data storage connected to the word lines and the bit lines, a refresh decision-making circuit that detects whether or not a refresh is requested for the plurality of memory cells based upon a control signal provided from the outside and makes a decision with regard to its mode, a refresh timer that is activated when the result of the decision-making performed by the refresh decision-making circuit indicate a self refresh mode to generate a timing signal, a generator that generates a counter control clock that is synchronous with the timing signal, a means for counter activation that outputs an activation signal set to a first potential when the result of the decision-making performed by the refresh decision-making circuit indicate a self refresh mode or a refresh mode other than the self refresh mode and set to a second potential if the result of the decision-making indicate neither the self refresh mode nor a refresh mode other than the self refresh mode and a refresh counter that is activated by the activation signal set to the first potential to generate and output a refresh address for a refresh in synchronization with the counter control clock, is provided.
The DRAM is further provided with an X address buffer having the activation signal input therein, that stores the refresh address when the activation signal is at the first potential and stores an X address provided from the outside if the activation signal is set to the second potential, a means for latching that latches block selection information provided from the outside with specific timing indicating whether or not it is necessary to refresh the block, an X pre-decoder that compares the block selection information latched by the means for latching with the refresh address stored at the X address buffer, outputs a pre-decode signal at the first potential containing information indicating a block specified by the refresh address that requires a refresh and sets the pre-decode signal to the second potential if the refresh address specifies a block that does not need to be refreshed and an X decoder that decodes the pre-decode signal at the first potential output by the X pre-decoder to select a word line corresponding to the memory cells within the block specified by the X pre-decoder with its word line selection operation prohibited if the pre-decode signal is set at the second potential.
In a fourth aspect, the block selection information is input via a pad for inputting/outputting the data from/to the outside or via a pad through which the X address is input from the outside in the DRAM provided in the first, second or third aspect.
In a fifth aspect, a shift register connected to the pad in the DRAM provided in the fourth aspect is provided instead of the means for latching, and the block selection information is latched by the shift register.
In a sixth aspect, a means for refresh mode setting that has a function of setting a first refresh mode for performing a selective block refresh and a second refresh mode for performing a refresh for all the blocks, outputs a pre-decode signal at either the first or the second potential from the X pre-decoder when the first refresh mode is set and provides a signal that prohibits the pre-decode signal from shifting to the second potential to the X pre-decoder when the second refresh mode is set, is provided in any of the DRAM achieved in the secondxcx9cfifth aspects.
In a seventh aspect, a selection signal indicating whether or not a refresh is necessary for each of a plurality of areas achieved by further dividing each of the blocks is input and the refresh is performed only for the memory cells in an area that requires a refresh within a block requiring the refresh in any of the DRAM achieved in the firstxcx9csixth aspects.
In an eighth aspect, the block selection information and the selection signal are input through a common pad and a means for switching that switches between the destination for the input block selection information and the destination for the input selection signal is provided in the DRAM achieved in the seventh aspect.
In a ninth aspect, a means for block selection information generation that pre-decodes the X address input from the outside via the pad and generates the block selection information based upon the results of decoding is provided in any of the DRAM achieved in the fourthxcx9ceighth aspects.
In the DRAM in the firstxcx9cninth aspects structured as described above, the block selection information indicating whether or not an individual block needs to be refreshed, which is provided from the outside, is latched, for instance, by the means for latching as in the first aspect. The means for operation prohibition compares the block selection signal with the refresh address, and the operation of the generator is halted if the refresh address indicates a block that does not require a self refresh. Thus, a refresh operation is not performed for blocks that do not need to be refreshed. Since the means for clock route changing provides the timing signal to the refresh counter instead of the counter control clock during this process, the refresh counter is allowed to generate a refresh address even while the generator is not engaged in an operation so that a self refresh for another block is sustained.
In the DRAM achieved in the second aspect, the block selection signal indicating whether or not the individual blocks need to be refreshed, which is provided from the outside, is latched by the means for latching. The X pre-decoder compares the block selection information and the refresh address if the refresh decision-making circuit specifies the self refresh mode. Then, if the refresh address specifies a block that requires a self refresh, the pre-decode signal is set to the first potential, whereas the pre-decode signal is set to the second potential and is provided to the X decoder if the refresh address specifies a block that does not require a self refresh. When the pre-decode signal is set to the first potential, the X decoder decodes the pre-decode signal to select memory cells inside the selected block, but it does not engage in a memory selection operation if the pre-decode signal is set to the second potential. Thus, a self refresh is performed only for the selected block.